Want to put a MC68000 on an FPGA? No worries, this is easy! OpenCores has already implemented this, look here!
20201119/DuckDuckGo tg68 core
20201119/https://opencores.org/projects/tg68
The license is GNU Lesser General Public License version 3, so if you have some Creative Commons Attribution Share-Alike 4.0 code, like from Steve Chamberlin’s FPGA IWM, then you can combine the whole product together under the license GNU General Public License version 3. Yeah, I know, it’s tricky, but at least it works. Yeah, and if you’re wondering about, Steve Chamberlin also implemented a Macintosh Plus clone on an FPGA, this involved writing FPGA cores for the support chips like the VIA. But, what license is that under? Since the TG68 core is under LGPLv3, this means the remainder of the whole linkage can potentially be proprietary. And since the license for the remainder is unspecified, we might as well just assume the remainder of the code is proprietary, given what we know about Steve Chamberlin.
20201119/https://github.com/steve-chamberlin/fpga-disk-controller
20201119/https://www.gnu.org/licenses/license-list.html
20201119/https://www.bigmessowires.com/plus-too/
20201119/https://www.bigmessowires.com/plustoo.zip
So, a problem I’m seeing stir up here… TG68 is written in VHDL, but some of my code is written in Verilog? How do you put the two together onto a single FPGA? No worries, you can instantiate Verilog from within VHDL. So, your master module that includes all the code of the FPGA will be written in VHDL, and your submodules can be in Verilog. Well, that being said, my understanding of the big thing to know about the two languages is that Verilog is simpler and more universal, whereas VHDL is more powerful. But, point in hand, Verilog is also more popular for relatively simple logic designs.
20201119/DuckDuckGo compile verilog and vhdl together fpga
20201119/https://www.fpgarelated.com/showthread/comp.arch.fpga/95756-1.php
20201119/DuckDuckGo convert verilog to vhdl
20201119/https://forums.xilinx.com/t5/Implementation/Convert-Verilog-code-to-VHDL-code/td-p/983469
20201119/DuckDuckGo instantiate verilog in vhdl
20201119/https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ism_p_instantiating_verilog_module_mixedlang.htm
20201119/https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ism_r_mixed_lang_boundary_mapping_rules.htm
20201119/https://stackoverflow.com/questions/48172504/can-a-verilog-module-be-instantiated-in-a-vhdl-module-using-entity-instantiation#48173849
One more thing, wondering how the high-speed timing on the Macintosh Plus and earlier work? The whole thing about shifting the phase of the high-speed timing, and READ PHASE, that is tricky. Well, shifting the phase is well-documented, but the READ PHASE portion? That I do not know about. But, this was a design made by Burrell using minimal logic from PAL chips, so it totally makes sense that he would prefer a software solution for the synchronization. Here is some great info about this.
20201119/http://www.1000bit.it/support/articoli/apple/mac128.pdf